Conventionally, three-dimensional (3D) integrated circuit (IC) devices have been fabricated to improve chip density, by initially forming individual circuit devices and subsequently stacking and bonding the chips together to form a multi-level chip stack or assembly. Consequently, the time, materials and process acts expended in carrying out individual chip fabrication, forming an assembly and electrically connecting the chips results in undesirably high cost. Moreover, stacking and electrical connection of the individually fabricated chips may lead to increased resistance and signal delay in the overall circuit due to undesirably long signal paths. Further, transmission of signals through wiring of one layer of the assembly may electrically interfere with wiring on other layers, e.g., cross-talk.
Another technique that has been suggested to increase chip density, for minimization of design dimension, is a so-called “bottom-up” approach. In this approach, circuits are fabricated conventionally on a base substrate, such as a silicon-on-insulator (SOI) wafer, followed by growth of successive layers of silicon on the wafer to provide an active surface and fabrication of additional circuit levels on each successive silicon layer prior to growth of the next-higher level. The process is repeated to create a device having a desired number of layers. One of the difficulties of this approach is that each circuit level, other than the last fabricated, is exposed to multiple thermal cycles as subsequent levels are formed. Further, due to the thermal cycling required by a bottom-up approach, suitable material choices for circuit structures are limited. Additionally, this approach requires an excessive amount of time as a consequence of growing each new layer of silicon on the base substrate.
Further, the foregoing approaches to multi-level circuit fabrication each require the use, and consumption, of a silicon wafer or other bulk substrate, which bulk substrate comprises a significant portion of the total cost of the fabrication process, on the order of twenty to thirty percent.
Accordingly, there are needs for processes to make 3D integrated circuits more efficiently and with reduced expense, while facilitating minimization of the overall dimensions of the device.